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CAT5132
15 Volt Digitally Programmable Potentiometer (DPPTM) with 128 Taps and 2-wire Interface
FEATURES
s 128 Resistor taps
DESCRIPTION
s Single linear Digitally Programmable Potentiometer The CAT5132 is a high voltage Digitally Programmable
Potentiometer (DPP) integrated with EEPROM memory and control logic to operate in a similar manner as a s End-to-end resistance of 10k, 50k & 100k mechanical potentiometer. The DPP consists of a series of resistive elements connected between two externally s Potentiometer control and memory access via 2 accessible end points. The tap points between each 2-wire interface (I C-like) resistive element are connected to the wiper output with s Nonvolatile memory storage for wiper settings CMOS switches. A separate 7-bit control register (WCR) s Automatic recall of saved wiper setting at power up independently controls the wiper tap switches for the s Special increment/decrement instruction mode for DPP. Associated with the control register is a 7-bit nonvolatile memory data register (DR) used for storing automatic trimming adjustments wiper settings. Writing to the wiper control register or the s VCC operation from 2.7 V to 5.5 V nonvolatile data register is via a 2-wire serial bus (I2Cs V+ (Analog Voltage Supply) operation from +8 V to like). +15V On power-up, WCR is set to mid scale (1000000) and s Standby current less than 15 A after the Power Supply becomes stable, the contents of s 100 year nonvolatile memory data retention the data register (DR) are transferred to the wiper control register (WCR) and the wiper is positioned to that s 10-pin MSOP package location. s Operating temperature of -40C to + 85C The CAT5132 comes with 2 voltage supply inputs: VCC, the digital supply voltage input and V+, an analog supply voltage input. These inputs allow the V+ to be as much APPLICATIONS as 10 volts higher than the VCC and allow the DPP s LCD screen adjustment terminal values to be as much as 15 volts above ground. s Volume control The CAT5132 can be used as a potentiometer or as a s Mechanical potentiometer replacement two-terminal variable resistor. It is intended for circuit level adjustments. It is supplied standard in the -40C to s Gain adjustment +85C industrial operating temperature range and offered s Line impedance matching in the 10-pin MSOP package. s VCOM setting adjustments
BLOCK DIAGRAM
SDA SCL A0 A1
VCC
V+ 127 RH
CONTROL LOGIC AND ADDRESS DECODE
127 RESISTIVE ELEMENTS
128 TAP POSITION DECODE CONTROL 7-BIT NONVOLATILE MEMORY REGISTER (DR) 7-BIT WIPER CONTROL REGISTER (WCR) 0
RL RW
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc. No. 25092, Rev. 00
CAT5132
PIN CONFIGURATION PIN DESCRIPTION
Pin Number
SDA GND VCC A1 A0 1 2 3 4 5 10 9 8 7 6 SCL V+ RL RW RH
Name SDA
Description Serial Data Input/Output - Bidirectional Serial Data pin used to transfer data into and out of the CAT5132. This is an Open-Drain I/O and can be wire OR'd with other Open-Drain (or Open Collector) I/Os. Ground Digital Supply Voltage (2.7V to 5.5V) Address Select Input to select slave address for 2-wire bus. Address Select Input to select slave address for 2-wire bus. High Reference Terminal for the potentiometer Wiper Terminal for the potentiometer Low Reference Terminal for the potentiometer Analog Supply Voltage for the potentiometer (+8.0V to 15.0V) Serial Bus Clock input for the 2-wire Serial Bus. This clock is used to clock all data transfers into and out of the CAT5132
1
2 3 4 5 6 7 8 9 10
GND VCC A1 A0 RH RW RL V+ SCL
MSOP 10-Pin Package
ORDERING INFORMATION
Prefix CAT Device # 5132 Suffix R -10 Resistance -10: 10k ohms -50: 50k ohms -100: 100k ohms TE13
Company ID
Product Number
Tape & Reel 2500 units/Reel
Package R: MSOP Z: MSOP (Green with Sn Lead Finish) GZ: MSOP (Green with NiPd Au Lead Finsh)
Notes: 1. The device used in the above example is a CAT5132R-10TE13 (MSOP, 10k ohms, Tape & Reel). 2. The Industrial Temperature range of -40C to +85C is standard on the above product.
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT5132
ABSOLUTE MAXIMUM RATINGS
Temperature Under Bias....................-55C to +125C Storage Temperature ........................ -65C to +150C Voltage on any SDA, SCL, A0 & A1 pins with respect to Ground (1)(2) .............................. -2.0V to VCC + 2.0V Voltage on RH, RL & RW Pins with respect to Ground .................................... -2.0V to "V+" + 1.0V VCC with respect to Ground ................... -2.0V to 7.0V V+ with respect to Ground ................... -2.0V to 16.0V Wiper Current (10 sec) ...................................... +6mA Lead Soldering temperature (10 sec) .............. +300C
RECOMMENDED OPERATING CONDITIONS
VCC = +2.7V to +5.5V V+ = 8.0V to +15V Operating Temperature Range: -40C to +85C
COMMENT Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol RPOT RPOT RPOT RTOL IW RW VTERM RES ALIN RLIN TCRPOT TCRatio CH/CL/CW fc Parameter Potentiometer Resistance (100k) Potentiometer Resistance (50k) Potentiometer Resistance (10k) Potentiometer Resistance Tolerance Power Rating Wiper Current Wiper Resistance Voltage on RW, RH or RL Resolution Absolute Linearity Relative Linearity
(2)
Test Conditions
Limits Min Typ 100 50 10 +20 Max
Units k k k % mW mA V % LSB LSB
(4) (4)
25* C IW = +1mA @ V+ = 12V IW = +1mA @ V+ = 8V GND = 0V; V+ = 8V to 15V RW(n)(actual) - RW(n)(expected)
(1) (1) (1) (5)
50 +3 70 110 GND 0.78 +1 +0.5 +300 30 10/10/25 0.4 150 200 V+
(3)
RW(n+1) - [RW(n)+LSB](5)
Temperature Coefficient of RPOT Ratiometric Temperature Coefficient Potentiometer Capacitances Frequency Response
ppm/* C ppm/* C pF MHz
RPOT = 50k
Notes: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer. 3. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. 4. LSB = (RHM - RLM)/127; where RHM and RLM are the highest and lowest measured values on the wiper terminal. 5. n = 1, 2, ..., 127
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 25092, Rev. 00
CAT5132
D.C. ELECTRICAL CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol ICC1 ICC2 ISB(VCC) ISB(V+) ILI ILO VIL VIH VOL1
Parameter Power Supply Current (Volatile Write/Read) Power Supply Current (Nonvolatile WRITE) Standby Current (VCC = 5V) V+ Standby Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage (VCC = 3.0)
Test Conditions FSCL = 400kHz, SDA Open, VCC = 5.5V, Input = GND FSCL = 400kHz, SDA Open, VCC = 5.5V, Input = GND VIN = GND or VCC , SDA = VCC VCC = 5V, V+ = 15V VIN = GND to VCC VOUT = GND to VCC
Min
Max 1 3.0 5 10 10 10
Units mA mA A A A A V V V
-1 VCC x 0.7 IOL = 3mA
VCC x 0.3 VCC + 1.0 0.4
CAPACITANCE
TA = 25C, f = 1.0MHz, VCC = 5.0V
Symbol CI/O CIN
Parameter Input/Output Capacitance (SDA) Input Capacitance (A0, A1, SCL)
Test Conditions VI/O = 0V (1) VIN = 0V (1)
Min
Max 8 6
Units pF pF
A.C. CHARACTERISTICS
VCC = 2.7 - 5.5V Symbol FSCL TI (1) tAA tBUF
(1)
Parameter (see Fig. 1) Clock Frequency Noise Suppression Time Constant at SCL & SDA Inputs SLC Low to SDA Data Out and ACK Out Time the bus must be free before a new transmission can start Start Condition Hold Time Clock Low Period Clock High Period Start Condition Setup Time (for a Repeated Start Condition) Data in Hold Time SDA and SCL Rise Time SDA and SCL Fall Time Stop Conditions Setup Time Data Out Hold Time
Min
Max 400 50 1
Units kHz ns s s s s s s ns
1.2 0.6 1.2 0.6 0.6 0 0.3 300 0.6 100
tHD:STA tLOW tHIGH tSU:STA tHD:DAT tR tF
(1) (1)
s ns s ns
tSU:STO tDH
Notes: 1. This parameter is tested initially and after a design or process change that affects the parameter.
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT5132
POWER UP TIMING (1)(2)
Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Min Max 1 1 Units ms ms
XDCP TIMING
Symbol tWRPO tWRL Parameter Wiper Response Time After Power Supply Stable Wiper Response Time After Instruction Issued Min 5 5 Max 10 10 Units s s
WRITE CYCLE LIMITS
Symbol tWR Parameter Write Cycle Time (see Fig. 2) Min Max 5 Units ms
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high and the device does not respond to its slave address.
RELIABILITY CHARACTERISTICS
Symbol NEND (1) TDR (1) VZAP (1) ILTH
(1)
Parameter Endurance Data Retention ESD Susceptibility Latch-Up
Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
Min 100,000 100 2000 100
Max
Units Cycles/Byte Years Volts mA
Notes: 1. This parameter is tested initially and after a design or process change that affects the parameter. 2. tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated.
TYPICAL PERFORMANCE CHARACTERISTICS
Resistance between RW and RL
12.000 10.000 8.000 6.000 4.000 2.000 0.000 0 16 32 48 64 Tap position 80 96 112 128
Icc2 (uA)
Icc2 (NV write) vs Temperature
400 350 300 250 200 150 100 50 0 -50 -30 -10 10 30 50 70 90 110 130 Temperature (C) Vcc = 2.7V Vcc = 5.5V
Vcc=2.7V; V+=8v Vcc=5.5V; V+=15V
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
RWL (Kohm)
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CAT5132
TYPICAL PERFORMANCE CHARACTERISTICS (CONT)
Absolute Linearity Error per Tap Position
1.000 0.800 0.600
Tamb = 25 C Rtotal = 10K Vcc=2.7V; V+=8v Vcc=5.5V; V+=15V
Relative Linearity Error
0.500 0.400 0.300
RLIN Error (LSB)
Tamb = 25 C Rtotal = 10K
Vcc=2.7V; V+=8V Vcc=5.5V; V+=15V
ALIN Error (LSB)
0.400 0.200 0.000 -0.200 -0.400 -0.600 -0.800 -1.000 0 16 32 48 64 Tap position 80 96 112 128
0.200 0.100 0.000 -0.100 -0.200 -0.300 -0.400 -0.500 0 16 32 48 64 Tap position 80 96 112 128
tF tLOW SCL tSU:STA tHD:STA
tHIGH tLOW
tR
tHD:DAT
tSU:DAT
tSU:STO
SDA IN tAA SDA OUT tDH tBUF
Figure 1. Bus Timing
SCL
SDA
8TH BIT BYTE n
ACK tWR STOP CONDITION START CONDITION ADDRESS
Figure 2. Write Cycle Timing
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT5132
SERIAL BUS PROTOCOL
The following defines the features of the 2-wire bus protocol: (1) Data transfer may be initiated only when the bus is not busy. (2) During a data transfer, the data line must remain stable whenever the clock line is high. Any changes in the data line while the clock is high will be interpreted as a START or STOP condition. The device controlling the transfer is a master, typically a processor or controller, and the device being controlled is the slave. The master will always initiate data transfers and provide the clock for both transmit and receive operations. Therefore, the CAT5132 will be considered a slave device in all applications. START Condition The START Condition precedes all commands to the device, and is defined as a HIGH to LOW transition of SDA when SCL is HIGH. The CAT5132 monitors the SDA and SCL lines and will not respond until this condition is met (see Fig. 3). STOP Condition A LOW to HIGH transition of SDA when SCL is HIGH determines the STOP condition. All operations must end with a STOP condition (see Fig. 3). Acknowledge After a successful data transfer, each receiving device is required to generate an acknowledge. The Acknowledging device pulls down the SDA line during the ninth clock cycle, signaling that it received the 8 bits of data (see Fig. 4). The CAT5132 responds with an acknowledge after receiving a START condition and its slave address. If the device has been selected along with a write operation, it responds with an acknowledge after receiving each 8-bit byte. When the CAT5132 is in a READ mode it transmits 8 bits of data, releases the SDA line, and monitors the line for an acknowledge. Once it receives this acknowledge, the CAT5132 will continue to transmit data. If no acknowledge is sent by the Master, the device terminates data transmission and waits for a STOP condition. Acknowledge Polling The disabling of the inputs can be used to take advantage of the typical write cycle time. Once the stop condition is issued to indicate the end of the host's write operation, the CAT5132 initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address. If the CAT5132 is still busy with the write operation, no ACK will be returned. If the CAT5132 has completed the write operation, an ACK will be returned and the host can then proceed with the next instruction operation.
SDA
SCL START CONDITION STOP CONDITION
Figure 3. Start/Stop Condition
SCL FROM MASTER
1
8
9
DATA OUTPUT FROM TRANSMITTER
DATA OUTPUT FROM RECEIVER START ACKNOWLEDGE
Figure 4. Acknowledge Condition
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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Doc No. 25092, Rev. 00
CAT5132
DEVICE DESCRIPTION
Access Control Register The volatile register WCR and the non-volatile register DR of CAT5132 are accessed only by addressing the volatile Access Register AR first, using the 3 byte I2C interface for all read and write operations (see Table 1). The first byte is the slave address/instruction byte (see details below). The second byte contains the address (02h) of the AR register. The data in the third byte controls which register WCR (80h) or DR (00h) is being addressed (see Figure 5). Slave Address Instruction Byte Description The first byte sent to the CAT5132 from the master processor is called the Slave/DPP Address Byte. The most significant five bits of the slave address are a device type identifier. These bits for the CAT5132 are fixed at 01010 (refer to Table 2). The next two bits, A1 and A0, are the internal slave address and must match the physical device address which is defined by the state of the A1 and A0 input pins to successfully address the CAT5132. Only the device with slave address matching the input byte will be accessed by the master. This allows up to 4 devices to reside on the same bus. The A1 and A0 inputs can be actively driven by CMOS input signals or tied to VCC or Ground. The last bit is the READ/WRITE bit and determines the function to be performed. If it is a "1" a read command is initiated and if it is a "0" a write is initiated. For the AR register only write is allowed. After the Master sends a START condition and the slave address byte, the CAT5132 monitors the bus and responds with an acknowledge (on the SDA line) when its address matches the transmitted slave address.
Table 1. Access Control Register
START ID4 ID3 ID2 ID1 ID0 Wb STOP
1st byte
ACK A1 A0
2nd byte
ACK
3rd byte WCR(80h) / DR (00h) selection 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
ACK
A R address - 02h 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0
ST ST
0 0
1 1
0 0
1 1
0 0
0 0
0 0
0 0
A A
A A
A A
SP SP
Table 2. Byte 1 Slave Address and Instruction Byte Device Type Identifier ID4 0 (MSB) ID3 1 ID2 0 ID1 1 ID0 0 Slave Address A1 X A0 X Read/Write R/W X (LSB)
BUS ACTIVITY: MASTER SDA LINE
SLAVE ADDRESS S T & INSTRUCTION A R FIXED T S
VARIABLE
AR REGISTER ADDRESS
WCR/DR SELECTION
S T O P P
A C K
A C K
A C K
Figure 5. Access Register Addressing Using 3 Bytes
Doc. No. 25092, Rev. 00
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
CAT5132
Wiper Control Register (WCR) Description The CAT5132 contains a 7-bit Wiper Control Register which is decoded to select one of the 128 switches along its resistor array. The WCR is a volatile register and is written with the contents of the nonvolatile Data Register (DR) on power-up. The Wiper Control Register loses its contents when the CAT5132 is powered-down. The contents of the WCR may be read or changed directly by the host using a READ/WRITE command after addressing the WCR (see Table 1 to access WCR). Since the CAT5132 will only make use of the 7 LSB bits (The first data bit, or MSB, is ignored) on write instructions and will always come back as a "0" on read commands.
A write operation (see Table 3) requires a Start condition, followed by a valid slave address byte, a valid address byte 00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge. At this time the data is written only to volatile registers, then the device enters its standby state. Table 3. WCR Write Operation
START ID4 ID3 ID2 ID1 ID0 Wb A1 A0
AR address - 02h 0 0 0 0 0 0 1 0 WCR(80h) selection 1 0 0 0 0 0 0 0
ST
0
1
0
1
0
0
0
0
A
A
A
SP
START
ST
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
0
0
A
X
X
X
X
X
X
X
X
ACK
A
slave address byte
WCR address - 00h
data byte
SP
An increment operation (see Table 4) requires a Start condition, followed by a valid increment address byte (01011), a valid address byte 00h. After each of the two bytes, the CAT5132 responds with an acknowledge. At this time if the data is high then the wiper is incremented or if the data is low the wiper is decremented at each clock. Once the stop is issued then the device enters its standby state with the WCR data as being the last inc/dec position. Also, the wiper position does not roll over but is limited to min and max positions. Table 4. WCR Increment/Decrement Operation
START ID4 ID3 ID2 ID1 ID0 Wb A1 A0
AR address - 02h 0 0 0 0 0 0 1 0
WCR(80h) selection 1 0 0 0 0 0 0 0
ST
START
0
1
0
1
0
0
0
0
A
A
A
SP
slave address byte 0 1 0 1 1 0 0 0
WCR address - 00h 0 0 0 0 0 0 0 0
increment (1) / decrement (0) bits 1 1 1 1 0 0 0 0
ST
A
A
SP
A read operation (see Table 5) requires a Start condition, followed by a valid slave address byte for write, a valid address byte 00h, a second START and a second slave address byte for read. After each of the three bytes, the CAT5132 responds with an acknowledge and then the device transmits the data byte. The master terminates the read operation by issuing a STOP condition following the last bit of Data byte. Table 5. WCR Read Operation
START ID4 ID3 ID2 ID1 ID0 Wb A1 A0
AR address - 02h 0 0 0 0 0 0 1 0 WCR(80h) selection 1 0 0 0 0 0 0 0
ST
0
1
0
1
0
0
0
0
A
A
A
SP
START
slave address byte 0 1 0 1 0 0 0 0
ACK
WCR address - 00h 0 0 0 0 0 0 0 0
ST
A
START
slave address byte 0 1 0 1 0 0 0 1 A 0 X X
data byte X X X X X
ST
SP
(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
STOP
9
STOP
Doc No. 25092, Rev. 00
ACK
ACK
1st byte
2nd byte
3rd byte
ACK
STOP
ACK
ACK
STOP
ACK
ACK
1st byte
2nd byte
3rd byte
ACK
STOP
ACK
ACK
STOP
ACK
ACK
1st byte
2nd byte
3rd byte
ACK
CAT5132
Data Register (DR) The Data Register (DR) is a nonvolatile register and its contents are automatically written to the Wiper Control Register (WCR) on power-up. It can be read at any time without effecting the value of the WCR. The DR, like the WCR, only stores the 7 LSB bits and will report the MSB bit as a "0". Writing to the DR is performed in the same fashion as the WCR except that a time delay of up to 5ms is experienced while the nonvolatile store operation is being performed. During the internal non-volatile write cycle, the device ignores transitions at the SDA and SCL pins, and the SDA output is at a high impedance state. The WCR is also written during a write to DR. After a DR WRITE is complete the DR and WCR will contain the same wiper position.
To write or read to the DR, first the access to DR is selected, see table 1 then the data is written or read using the following sequences. A write operation (see Table 6) requires a Start condition, followed by a valid slave address byte, a valid address byte 00h, a data byte and a STOP condition. After each of the three bytes the CAT5132 responds with an acknowledge. At this time the data is written both to volatile and non-volatile registers, then the device enters its standby state. Table 6. DR Write Operation
START ID4 ID3 ID2 ID1 ID0 Wb A1 A0
AR address - 02h 0 0 0 0 0 0 1 0 DR(00h) selection 0 0 0 0 0 0 0 0
ST
0
1
0
1
0
0
0
0
A
A
A
SP
START
ST
0
1
0
1
0
0
0
0
A
0
0
0
0
0
0
0
0
A
X
X
X
X
X
X
X
X
ACK
A
slave address byte
DR address - 00h
data byte
SP
A read operation (see Table 7) requires a Start condition, followed by a valid slave address byte, a valid address byte 00h, a second Start and a second slave address byte for read. After each of the three bytes the CAT5132 responds with an acknowledge and then the device transmits the data byte. The master terminates the read operation by issuing a STOP condition following the last bit of Data byte. Table 7. DR Read Operation
START ID4 ID3 ID2 ID1 ID0 Wb A1 A0
AR address - 02h 0 0 0 0 0 0 1 0
DR(00h) selection 0 0 0 0 0 0 0 0
ST
START
0
1
0
1
0
0
0
0
A
A
A
SP
slave address byte 0 1 0 1 0 0 0 0
ACK
DR address - 00h 0 0 0 0 0 0 0 0
STOP
ST
START
A
slave address byte 0 1 0 1 0 0 0 1 A 0 X X
data byte X X X X X
ST
SP
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
STOP
ACK
ACK
1st byte
2nd byte
3rd byte
ACK
STOP
ACK
ACK
STOP
ACK
ACK
1st byte
2nd byte
3rd byte
ACK
CAT5132
POTENTIOMETER OPERATION
Power-On The CAT5132 is a 128-position, digital controlled potentiometer. At power-up the device turns on at the mid-point wiper location (64) until the wiper register can be loaded with the nonvolatile memory location previously stored in the device. After the nonvolatile memory data is loaded into the wiper register the wiper location will change to the previously stored wiper position. The end-to-end nominal resistance of the potentiometer has 128 contact points linearly distributed across the total resistor. Each of these contact points is addressed by the 7 bit wiper register which is decoded to select one of these 128 contact points. Each contact point generates a linear resistive value between the 0 position and the 127 position. These values can be determined by dividing the end-to-end value of the potentiometer by 127. In the case of the 10k potentiometer~79 is the resistance between each wiper position. However in addition to the ~79 for each resistive segment of the potentiometer, a wiper resistance offset must be considered. Table 8 shows the effect of this value and how it would appear on the wiper terminal. This offset will appear in each of the CAT5132 end-toend resistance values in the same way as the 10k example. However resistance between each wiper position for the 50k version will be ~395 and for the 100k version will be ~790. Table 8. Potentiometer Resistance and Wiper Resistance Offset Effects
Position 00 01 63 127 Typical RW to RL Resistance for 10k DPP 70 or 149 or 5,047 or 10,070 or 0 + 70 79 + 70 4,977 + 70 10,000 + 70
Position 00 64 126 127
Typical RW to RH Resistance for 10k DPP 10,070 or 5,047 or 149 or 70 or 10,000 + 70 4,977 + 70 79 + 70 0 + 70
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Doc No. 25092, Rev. 00
CAT5132
PACKAGE OUTLINES 10-LEAD MSOP
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(c) 2005 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
REVISION HISTORY
Date 09/12/2005 Rev. 00 Reason Initial Issue
Copyrights, Trademarks and Patents Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
DPP TM AE2 TM MiniPotTM
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents issued to Catalyst Semiconductor contact the Company's corporate office at 408.542.1000.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a situation where personal injury or death may occur. Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale. Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate typical semiconductor applications and may not be complete.
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Publication #: Revison: Issue date:
25092 00 09/12/05

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